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DATA SHEET
MOS INTEGRATED CIRCUIT
PD9930
LINEAR CODEC FOR DIGITAL CELLULAR TELEPHONE
The PD9930 is a +3 V single power operation, low power consumption linear CODEC LSI developed for digital cellular telephone use. CODEC has a wide dynamic use. This IC also features a microphone/receiver amplifier, a tone generator, DAI (Digital Audio Interface: conforming to GSM11.10), and a power-saving function. These functions can be controlled by microcontroller. In addition, 21 mW (TYP.) low power consumption is enabled during 3 V operation.
FEATURES
* +3 V single power supply * Low power consumption In operation: 7 mA (TYP.) (VDD = 3 V) In stand-by mode: 50 A (TYP.) (VDD = 3 V) * CODEC * 13-bit precision linear coding * Transmission level can be controlled by microcontroller. * Analog input/output funciton * Low noise microphone amplifier * High output receiver amplifier Piezo-electric receiver can be directly driven. Gain canbe controlled by microcontroller. * On-chip amplifier for accessory input/output * Tone generator * Frequency, generating pattern and gain can be controlled by microcontroller. * DTMF generation function * Various service tone generation function * GSM triple tone generation function * Desired tone frequency can be registered (0.3 to 3.4 kHz) * DAI * Conforming to GSM11.10 * Test mode can be set by terminal or microcontroller command. * Stand-by mode * Rise time at time of stand-by clearing: 30.5 ms (TYP.) * Master clock generation PLL (external clock input: 8 kHz) * Tone interrupt pattern output function * Ringer output function
ORDERING INFORMATION
Part Number PD9930G-22 Package 44-pin plastic QFP (10 x 10 mm)
The information in this document is subject to change without notice. Document No. S11616EJ2V0DS00 (2nd edition) (Previous No. IC-3342) Date Published November 1996 N Printed in Japan The mark shows major revised points.
(c)
1994,1996
2
RESETB MIXI MICO (15 to 33 dB) MICI- MICI+ Microphone amplifier - + Digital signal processor PLL Pre-Filter + Mixer 0 or -3 dB
Voice send Digital Gain Cont. 0 to -2.8 dB (0.4 dB steps)
BLOCK DIAGRAM
REQB FSYNC (8 kHz)
A/D
Transmit BPF
(to XACOMO) XAUXO (0 to 10 dB) XAUXI-
SCLK (256 kHz) SEN DSP INTERFACE SO SI
Accessory input amplifier - + to Vref
Post Filter 1 (Accessory output amplifier) 0 dB fix
RAUXO
D/A REC1O
Post Filter 2 (Receiver amplifier 1) 0 to -31 dB (1 dB steps)
Receive LPF
Voice receive Digital Gain Cont. 0 to -2.4 dB (0.8 dB steps)
DSPSEL
REC2I- REC2O-
Receiver drive amplifier (Receiver amplifier 2) - +
MICROCONTROLLER INTERFACE Sign code output
Tone Gain Cont. 0 to -30 dB (1 dB steps) -38.5 dB Tone Generator
MCLK MSTR MDAT
to Vref
REC2O+
- + to Vref DAI (GSM11. 10)
DCLK DO DI TC1 TC2 DRSTB Tone Interval Generation
XACOMI XACOMO Vcombuff RACOMO RACOMI Vref
TIMER
RINGER
Low-current drive LED
PD9930
PD9930
PIN CONFIGURATION (Top View) 44-pin plastic QFP (10 x 10 mm)
RACOMO
XACOMO
REC2O+
REC2O-
RACOMI
XACOMI
XAUXI-
XAUXO
REC2I-
ICNote
33 REC1O RAUXO AVDD1 AVDD2 DVDD SEN SI SO SCLK TEST MSTR 34 35 36 37 38 39 40 41 42 43 44 1
32
31
30
29
28
27
26
25
24
23 22 21 20 19 18 17 16 15 14 13 12 MICO MICI- MICI+ AGND4 AGND3 AGND2 AGND1 DGND FSYNC RESETB REQB
2
3
4
5
6
7
8
9
10
11
DI
DO
TC1
TC2
TIMER
RINGER
MDAT
DRSTB
MCLK
DCLK
Note Internal connection; leave unconnected
DSPSEL
MIXI
3
PD9930
Pin Name
AGND1-AGND4 AVDD1, AVDD2 DCLK DGND DI DO DRSTB DSPSEL DVDD FSYNC IC MCLK MDAT MICI+ MICI- MICO MIXI MSTR RACOMI RACOMO RAUXO REC1O REC2I- REC2O+ REC2O- REQB RESETB RINGER SCLK SEN SI SO TC1, TC2 TEST TIMER XACOMI XACOMO XAUXI- XAUXO : Analog Ground : Analog Power Supply : DAI (Digital Audio Interface) Clock Output : Digital Ground : DAI Serial Input : DAI Serial Output : DAI Reset : Digital Signal Processor Select : Digital Power Supply : Frame Synchronization Signal Input : Internally Connected : Microcontroller Synchronous Clock : Microcontroller Serial Data : Microphone Amplifier Input Non-Inverted : Microphone Amplifier Input Inverted : Microphone Amplifier Output : Mixer Input : Microcontroller Strobe : Receive Common Reference Voltage Input : Receive Common Reference Voltage Output : Receive Auxiliary Amplifier Output : Receive Amplifier 1 Output : Receive Amplifier 2 Input Inverted : Receive Amplifier 2 Output Non-Inverted : Receive Amplifier 2 Output Inverted : Request : Reset : Ringer : Serial Data Synchronous Clock Output : Serial Data Output Enable : Serial Data Input : Serial Data Output : DAI Mode Control : Test : Timer : Transmit Common Reference Voltage Input : Transmit Common Reference Voltage Output : Transmit Auxiliary Amplifier Input Inverted : Transmit Auxiliary Amplifier Output
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PD9930
CONTENTS
1. PIN FUNCTIONS ........................................................................................................................... 6
1.1 LIST OF PIN FUNCTIONS ..................................................................................................................... 6 1.2 PIN EQUIVALENT CIRCUIT .................................................................................................................. 8
2. BLOCK FUNCTIONS ..................................................................................................................... 9
2.1 CODEC .................................................................................................................................................... 9 2.1.1 Audio Codec .............................................................................................................................. 9 2.1.2 Audio Analog Input .................................................................................................................. 9 2.1.3 Audio Analog Output ............................................................................................................. 10 2.1.4 Audio Digital Accessory Output ........................................................................................... 11 2.1.5 Audio Digital Signal Processor ............................................................................................ 11 2.1.6 Power Up/Down Control ........................................................................................................ 12 2.1.7 Microcontroller Interface ....................................................................................................... 18 2.1.8 DSP Interface .......................................................................................................................... 19 2.1.9 DAI (Digital Audio Interface) ................................................................................................. 22
3. TONE INTERVAL OUTPUT FUNCTION (TIMER TERMINAL) ................................................. 29 4. INTERNAL CONTROL FUNCTIONS ...........................................................................................30
4.1 SEND/RECEIVE GAIN CONTROL ...................................................................................................... 30 4.1.1 Voice Send Analog Gain/Receiver Amplifier 2 Control Register (TXGCR) .................... 32 4.1.2 Voice Receive Analog Gain Control Register (RXGCR) ................................................... 33 4.1.3 Voice Send/Receive Digital Gain Control Register (DGGSR) .......................................... 35 4.2 DIGITAL INPUT/OUTPUT CONTROL ................................................................................................. 37 4.2.1 Digital Signal Processing Control Register (DSPCR) ....................................................... 38 4.3 TONE CONTROL .................................................................................................................................. 40 4.3.1 Tone Frequency Selection Register (FRQSR) .................................................................... 43 4.3.2 Expanded Tone Registers (EXPR1, EXPR2) ....................................................................... 45 4.3.3 Tone Control Register (TONCR) ........................................................................................... 47 4.3.4 Tone Gain Control Register (TNGCR) ................................................................................. 48 4.4 TEST MODE CONTROL ...................................................................................................................... 50 4.4.1 Test Control Register (TSTCR) ............................................................................................. 52
5. ELECTRICAL CHARACTERISTICS ............................................................................................53 6. APPLIED CIRCUIT EXAMPLE .................................................................................................... 73 7. PACKAGE DRAWINGS ............................................................................................................... 74 8. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 75
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PD9930
1. PIN FUNCTIONS
1.1 LIST OF PIN FUNCTIONS Table 1-1 List of Pin Functions (1/2)
Pin No. 1 2 3 4 5 Pin Name MDAT MCLK DRSTB DI DO Input/Output Input Input Input Input Output Microcontroller interface serial input Microcontroller interface clock input DAI (Digital Audio Interface) reset input This is reset at low level. Internally pulled high. DAI serial input Internally pulled high. DAI serial output Hi-Z in normal operation (TC1 = TC2 = low level) 6 7 DCLK TC1 Output Input DAI clock output (104 kHz) Hi-Z in normal operation DAI mode control Selection of test mode specified by GSM11.10 in combination with TC1 and TC2 L: Low level H: High level TC2 L L H H TC1 L H L H Test mode specification Normal operation Speech encoder test mode Speech decoder test mode Acoustic device test mode Function
8
TC2
Input
TC1 and TC2 pins are internally pulled down. 9 10 11 TIMER RINGER DSPSEL Output Output Input Timer output. Output of rectangular wave synchronized with tone intermittent pattern. Ringer tone output. Output of rectangular wave synchronized with tone frequency. Selection of DSP interface input/output timing mode. Connect to VDD or GND. (VDD = mode 1, GND = mode 2) Input of DSP interface data transmit request signal. Serial data can be input/output at low level. System reset input. This is reset at low level. Initializes all control registers. Reset when turning power on. Send/receive frame synchronization signal (8 kHz) input Digital ground. Connect to a digital ground line near PD9930 pins. Analog ground. Connect to an analog ground line near PD9930 pins.
12 13 14 15 16 17 18 19 20 21 22 23 24
REQB RESETB FSYNC DGND AGND1 AGND2 AGND3 AGND4 MICI+ MICI- MICO MIXI XAUXO
Input Input Input -- -- -- -- -- Input Input Output Input Output
Microphone amplifier non-inverted input Microphone amplifier inverted input Microphone amplifier output. Connect microphone amplifier gain adjust resistor. Outputs sidetone signal to REC2I- pin. Pre-filter + mixer input Accessory input amplifier output. Connect accessory input amplifier gain adjust resistor.
6
PD9930
Table 1-1 List of Pin Functions (2/2)
Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name XAUXI- XACOMI XACOMO RACOMO RACOMI REC2O+ REC2O- IC REC2I- REC1O RAUXO AVDD1 AVDD2 DVDD SEN SI SO SCLK TEST MSTR Input/Output Input Input Output Output Input Output Output -- Input Output Output -- -- -- Output Input Output Output Input Input Digital power. Connect to a digital power supply line near PD9930 pins. DSP interface enable signal output DSP interface serial input DSP interface serial output DSP interface clock output (256 kHz) Set at high level Microcontroller interface strobe signal input Function Accessory input amplifier inverted input Voice send internal reference voltage input Voice send internal reference voltage (1.2 V) output Voice receive internal reference voltage (1.2 V) output Voice receive internal reference voltage input Receiver amplifier 2 non-inverted output Receiver amplifier 2 inverted output Internal connection; leave unconnected Receiver amplifier 2 inverted input Connect sidetone gain adjust resistor. Receiver amplifier 1 output Accessory output amplifier output Analog power. Connect to an analog power supply line near PD9930 pins.
Caution Short-circuit the XACOMI and XACOMO pins at a location as close to the pins of the PD9930 as possible. Connect a capacitor (chip capacitor or electrolytic capacitor) between this short-circuited portion and analog ground. The same applies to the RACOMI and RACOMO pins. The transmission/reception level is determined by these reference pins. Therefore, make sure that these pins are not affected by noise or fluctuation of ground potential due to current.
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PD9930
1.2 PIN EQUIVALENT CIRCUIT
Type 1 AVDD Type 2 AVDD
Analog input To internal circuit
Analog input To internal circuit
AGND Pin Name MICI+, MICI-, XAUXI-, REC2I- Type 3 AVDD
AGND Pin Name MIXI, XACOMI, RACOMI Type 4 DVDD
Analog output From internal circuit
CMOS input To internal circuit
AGND Pin Name MICO, XAUXO, XACOMO, RACOMO, REC2O+, REC2O-, REC1O, RAUXO Type 5 DVDD Mask input CMOS input To internal circuit CMOS input
DGND Pin Name MDAT, MCLK, DSPSEL, REQB, RESETB, FSYNC, TEST, MSTR Type 6
Note
DVDD
To internal circuit
DGND DGND Pin Name SI Type 7 Note DVDD DVDD Pin Name TC1, TC2 Type 8 P CMOS input To internal circuit CMOS output From internal circuit N DGND Pin Name TIMER, RINGER, SEN, SO, SCLK DVDD P CMOS output From internal circuit N DGND Pin Name DO, DCLK Enable signal DVDD
DGND Pin Name DRSTB, DI Type 9
Note In normal mode, set the output of drive IC side to high impedance for reducing power consumption.
8
PD9930
2. BLOCK FUNCTIONS
2.1 CODEC 2.1.1 Audio Codec Audio analog signal and linear code conversion. * Input/output format: 16 bits (2's complement) * Accuracy: 13 bits 2.1.2 Audio Analog Input Includes microphone input and accessory input. (1) Microphone amplifier Amplifiers differential input signals from the microphone to the required gain. (2) Accessory input amplifier Amplifiers the accessory input signal to the required gain. (3) Pre-filter + mixer Selects the output signal of microphone amplifier and accessory input amplifier, and inputs these to A/D converter after controlled gain. Table 2-1 Analog Input Function
Amplifier Function Gain setting method Gain setting range
Microphone Amplifier External resistor 15 to 33 dB R2 20 log (dB) R1 50 k (Including gain setting resistance) 20 pF 0.6 V0-p
Accessory Input Amplifier External resistor 0 to 10 dB R3 20 log (dB) R4 300 k (Including gain setting resistance) 20 pF 0.6 V0-p
Pre-filter + Mixer Microcontroller command 0 or -3 dB
Minimum resistive load Maximum capacitive load Maximum output level
-- -- --
Figure 2-1 Analog Input Block
MIXI MICO (15 to 33 dB) R2 R1 R1 (to XACOMO) (0 to 10 dB) R3 R4 to Vref XAUXO XAUXI- - + MICI- MICI+
Microphone amplifier
- +
Pre-filter + mixer 0 or -3 dB
Accessory input amplifier
9
PD9930
2.1.3 Audio Analog Output Includes receiver output and accessory output. Sidetone addition is also possible. (1) Post filter 2 (receiver amplifier 1) This circuit adjusts the gain of D/A differential output signal (volume control), and then converts it to single output signal. (2) Receiver drive amplifier (receiver amplifier 2) This is differential output amplifier that can directly drive a piezo-electric receiver (when using a dynamic receiver, an additional external amplifier is necessary). The sidetone is added in this circuit. (3) Post filter 1 (accessory output amplifier) This circuit converts D/A differential output signal to single output signal. Connected to the earphone of the head set (capacitance load), etc. Table 2-2 Analog Output Functions
Amplifier Function Gain setting method Gain setting range
Receiver Amplifier 1 Microcontroller command 0 to -31 dB (1 dB steps)
Receiver Amplifier 2 External resistor Voice receive signal gain: - to + 10 dB 20 log R3 (dB) + 6 dBNote R2 Sidetone signal gain: - to + 3 dB R3 20 log (dB) + 6 dBNote R1
Accessory Output Amplifier -- --
Minimum resistive load Maximum capacitive load Maximum output level
100 k 20 pF 0.6 V0-p
2 k 60 nF 4 Vp-p (Differential output)
100 k 100 pF 0.6 V0-p
Note Conversion result (single output differential output) Figure 2-2 Analog Output Block
RAUXO
Post filter 1 (accessory output amplifier) 0 dB fix Post filter 2 (receive amplifier 1) 0 to -31 dB (1 dB steps) Receiver drive amplifier (receiver amplifier 2) - +
REC1O
R2 Sidetone signal R1 R3 REC2I- REC2O-
to Vref
REC2O+
- + to Vref
10
PD9930
2.1.4 Audio Digital Accessory Output (1) Ringer output (RINGER pin) * Outputs rectangular waves of the same signal frequency as tone signal frequency. * The output is controlled by turning off power to the output buffer with a control register. Figure 2-3 RINGER Output
RAUXO (Tone output)
RINGER
The RINGER signal tends to bounce when the tone output (RAUXO) signal crosses its zero level, and this tendency increases as the tone output gain decreases (lower than 0 dB). When using RINGER pin, tune the tone output gain by TNGCR (Tone gain control register) to 0 dB. (2) Timer (tone interval) output (TIMER pin) Outputs rectangular waves of the same pattern as the tone signal interrupt pattern. This is used to make the LED blink in synchronization with the ringer tone. Figure 2-4 Digital Accessory Output Waveform
REC10 RAUXO (Tone output)
RINGER
TIMER
2.1.5 Audio Digital Signal Processor Send signal digital BPF processing, receive signal digital LPF processing, transmission level (digital gain) control, and tone generation processing. (1) Voice send signal digital gain fine adjustment function Performs gain fine adjustment for voice send signal by digital coefficient multiplication. Together with prefilter gain adjustment, fine adjustment is possible at a width of 5.8 dB. (2) Voice receive signal digital gain fine adjustment function Performs fine adjustment of gain for voice receive signal by digital coefficient multiplication. (3) Tone generation function Generates single-tone and dual-tone audible signals. Tone frequency, interrupt pattern, gain, generation/stop can be controlled by microcontroller command. GSM triple tone can be generated by special command.
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PD9930
Table 2-3 Digital Gain Control Functions
Voice Send Signal Gain Control Voice Receive Signal Gain Control Gain setting method Gain setting range Microcontroller command 0 to -2.8 dB (0.4 dB steps) Microcontroller command 0 to -2.4 dB (0.8 dB steps) Tone Gain Control Microcontroller command 0 to -30 dB (1 dB steps), -38.5 dB
2.1.6 Power Up/Down Control The PD9930 includes a power down function for reducing power consumption. Power down control is by the two methods described below. (1) Input/output amplifier power up/down control Power up/down for both the input and output amplifiers can be controlled. When the power down function is used for all input amplifiers, both pre-filter and A/D enter the power down state. When the power down function is used for the accessory output amplifier and the receiver 1 amplifier, the D/A also enters power down state. (2) Stand-by mode Low power consumption can be realized in the mode in which all chip operation is stopped. The stand-by mode is set by power down command. Operation restarts by power up command. The following control registers are used to enable the control described above.
Control Method Power up/down control of input/output amplifier (not including receiver amplifier 2) Power up/down control of receiver amplifier 2 Set/clear of standby mode Registers Used Input/output amplifier control register (AMPCR) Send analog gain/receiver amplifier 2 control register (TXGCR) Power up control command (PUPCMD) Power down control command (PDWCMD)
An outline diagram of power down control is shown in Figure 2-5.
12
PD9930
Figure 2-5 Power Down Control
Register address 0 0 0
AMPCR MICPDB XAUXPDB REC1PDB RAUXPDB RINGPDB TXGCR 1 1 0 REC2PDB TXAG
HEXNote
Register address 0 0 0
Power up command 0 1 1 1 1 0 -- --
M 78H
L 1EH
Power down command 0 1 1 1 0 0 -- --
HEXNote
M 70H
L 0EH
Note M: HEX value with MSB first L: HEX value with LSB first
PLL Microphone input - + Stand-by Stand-by "1" = Power ON MICPDB Pre-filter + mixer A/D
to XACOMI Accessory input - + to Vref When all input amplifiers are in the power down state, these also enter power down state.
"1" = Power ON XAUXPDB
Digital signal processor
Accessory output - + "1" = Power ON RAUXPDB Receiver 1 - + "1" = Power ON REC1PDB Receiver 2 - + to Vref
Stand-by
D/A
Stand-by When both accessory output and receiver 1 amplifiers are in the power down state, these also enter power down state. Stand-by "1" = Power ON - + to Vref REC2PDB
Ringer output Stand-by "1" = Ringer output RINGPDB
Caution MICPDB and XAUXPDB cannot enter the power up state at the same time (MICPDB = XAUXPDB = "1").
13
PD9930
(3) Input/output amplifier control register (AMPCR) This is a 5-bit register for power up/down control of each input/output amplifier (not including receiver amplifier 2), and for ringer output ON/OFF control. Remark For information on power up/down control of receiver amplifier 2, refer to 4.1.1 Voice Send Analog Gain/ Receiver Amplifier 2 Control Register (TXGCR). Figure 2-6 Input/Output Amplifier Control Register
Register address D7 0 D6 0 D5 0 D4 D3 AMPCR D2 D1 D0
MICPDB XAUXPDB REC1PDB RAUXPDB RINGPDB
MICPDB 0 1
Microphone amplifier power control Power down Power up
XAUXPDB Accessory input amplifier power control 0 1 Power down Power up
REC1PDB Receiver amplifier 1 power control 0 1 Power down Power up
RAUXPDB Accessory output amplifier power control 0 1 Power down Power up
RINGPDB Ringer output control 0 1 Sets output at low level. Output enable
Remarks 1. In the stand-by mode, all amplifiers enter the power down state regardless of input/output control register settings. However, register contents are held unless reset or written, so when the stand-by mode is cleared by power up command, the command prior to the stand-by mode is resumed. 2. The microphone and accessory amplifiers cannot enter the power up (D4 = D3 = "1") state at the same time.
14
PD9930
Table 2-4 Function Specification by Input/Output Amplifier Control Register
Register address AMPCR Microphone Accessory Receiver Accessory amplifier input amplifier amplifier 1 output amplifier Ringer output X X X X X X X X X X X X X X X X O O O O O O O O X X X X X X X X O O O O O O O O X X X X X X X X X X X X O O O O X X X X O O O O X X X X O O O O X X O O X X O O X X O O X X O O X X O O X X O O Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output HEXNote M L Remarks At reset
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
00H 00H 01H 80H 02H 40H 03H C0H 04H 20H 05H A0H 06H 60H 07H E0H 08H 10H 09H 90H 0AH 50H 0BH D0H 0CH 30H 0DH B0H 0EH 70H 0FH F0H 10H 08H 11H 88H 12H 48H 13H C8H 14H 28H 15H A8H 16H 68H 17H E8H
Note M: HEX value with MSB first L: HEX value with LSB first Remark O: Power up X: Power down
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PD9930
(4) Power up/down command (PUPCMD/PDWCMD) The stand-by mode is set and cleared by the following two special commands. When resetting, the stand-by mode is set. Figure 2-7 Power Down Command (Sets to stand-by mode)
D7 PDWCMD 0
D6 1
D5 1
D4 1
D3 0
D2 0
D1 X
D0 X
Remark X: Don't Care Figure 2-8 Power Up Command (Clears stand-by mode)
D7 PUPCMD 0
D6 1
D5 1
D4 1
D3 1
D2 0
D1 X
D0 X
Remark X: Don't Care Power up/down timing
Power up command FSYNC Power down command
COUNT
0
1
2
3
238
239
240
241
0
0
ANAPWD
CLKPWD
DSPPWD
Remarks COUNT:
Internal counter (counts with an 8-kHz internal clock)
ANAPWD: Analog power down (power down when high) CLKPWD: Clock power down (power down when high) DSPPWD: Signal processing power down (power down when high)
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PD9930
(5) Power up/down sequence (a) Power down sequence
Power down command execution
Digital signal processing (filter operation, tone generation operation) operation stop
Clock (internal clock, serial clock) power down
Analog (PLL, all amplifiers) power down
(b) Power up sequence
Power up command execution
Analog and PLL operation start
PLL clock stabilization
Clock operation start
Digital signal operation start
Remarks 1. The DSP interface serial input/output operation does not stop or start when switching to power up/down. 2. Rising time from standby mode to normal operation mode is about 30.5 ms after execution of the power up command. 3. FSYNC can be stopped at power down. However, input of the FSYNC clock is necessary during operation and in the above sequence.
17
PD9930
2.1.7 Microcontroller Interface The PD9930 can control internal functions by microcontroller command. A clock synchronous serial I/O is incorporated to receive command. A clocked serial interface is provided to receive microcontroller commands. A microcontroller connection example is shown in Figure 2-9. 8-bit length data is received by the serial clock (MCLK), serial input (MDAT), and strobe input (MSTR) lines Note. The timing chart is shown in Figure 2-10. By reading data to the internal shift register and setting MSTR to high level at the MCLK rising point, it is latched to the internal control register. Data transfer must be made with LSB first. Note When 8 bits or more (9 MCLK clocks or more) data is input, the last 8-bit which is input immediately before the active edge of MSTR is recognized as a control command. Figure 2-9 Example of Connection with Microcontroller
Microcontroller Serial I/O SO SCK PORT
PD9930
Microcontroller I/F MDAT MCLK MSTR
Figure 2-10 Microcontroller Interface Timing Chart
MCLK
MDAT
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
MSTR
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PD9930
2.1.8 DSP Interface A clock synchronous serial I/O is built-in to exchange voice send/receive coding data with an external DSP. 16-bit data is transferred at 8 kHz by the serial clock (SCLK = 256 kHz), serial input (SI), serial output (SO), and enable output (SEN) lines. The REQB is a terminal for allowing/inhibiting data transmission. There are two modes for data input and output timing, and either can be selected by the DSPSEL terminal. Select the mode matching the DSP serial interface input/output timing. Data format is as follows: Both SO output and SI input are in 2's complement format with MSB first. Figure 2-11 Data Format in DSP Interface
SO output D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Coding data (13 bits) Sign bit Invalid data
Remark A full code is output when the SO pin is +3.17 dBm0 (A/D 1.2 Vp-p).
SI input
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Coding data (15 bits) Sign bit
Remark When a full code is input to the SI pin, the accessory output is 1.2 Vp-p. Table 2-5 DSP Input/Output Timing Mode Selection
Pin input DSPSEL H L MODE1 MODE2
Mode
Table 2-6 Allowing Data Transmission
REQB pin Input L H Data Transmission Data transmission is allowed. Enable signal (SEN) is output at rising edge of FSYNC (8 kHz), and data input/output is started. Enable signal is not output and data are not input or output.
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PD9930
Figure 2-12 Example of Connection with DSP (Mode 1)
DSP Serial I/O SCK enable SI SO PORT VDD DSPSEL Note
PD9930
DSP I/F SCLK SEN SO SI REQB FSYNC 8 kHz
Note When using with mode 2, connect DSPSEL to GND.
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PD9930
Figure 2-13 DSP Interface Timing Chart (a) Mode 1 (DSPSEL = VDD)
REQB
125 s FSYNC (8 kHz)
SEN
SCLK (256 kHz)
SO
D15
D14
D2
D1
D0
D15
D14
D13
SI
don't care
D15
D14
D2
D1
D0
don't care
D15
D14
D13
(b) Mode 2 (DSPSEL = GND)
REQB
125 s FSYNC (8 kHz)
SEN
SCLK (256 kHz)
SO
D15
D14
D2
D1
D0
D15
D14
D13
SI
don't care
D15 D14
D13
D2
D1
D0
don't care
D15
D14
D13
D12
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PD9930
2.1.9 DAI (Digital Audio Interface) Has a on-chip circuit enabling DAI functions specified in GSM11.10. The receive system has a on-chip LPF only. If a BPF is necessary, it should be mounted externally. System configuration at the time of DAI test mode is shown in Figure 2-15. The DAI terminal is connected to the system simulator via the pin 25 DSUB socket. The test mode can be selected by terminals TC1 or TC2, or by microcontroller command. DAI mode should be set after completing power-up operation (30.5 ms after executing power-up command). When changing the modes from DAI to normal, either of the following operations should be executed. * After specifying normal mode, input the DAI reset signal (DRSTB = low). * Input reset signal (RESETB = low). When specifying by command, test control register mode specification bits (ITC1, ITC2) are used (Refer to 4.4.1 Test Control Register (TSTCR).). Timing for each mode is shown in Figures 2-16 through 2-20. For operation at the time of each mode, refer to Figure 4-13 Test Mode Operation. Table 2-7 DAI Test Mode Specification
TC2 TC1 (ITC2) (ITC1) 0 0 Test mode specification Normal operationNote Function
Normal operation. This mode is set at system reset (when RESETB = low) regardless of status of TC1 and TC2. Outputs data input from DI pin to DSP (speech encoder) from SO pin. Input is started at rising edge of first FSYNC (8-kHz external clock input) after execution of mode specification, and outputting data to DSP is started at next rising edge of FSYNC. Outputs speech decoder output data input from SI pin from DO pin. Inputting data from DSP is started at rising edge of first FSYNC (8-kHz external clock input) after execution of mode specification, and data is output from DO pin at next rising edge of FSYNC.
0
1
Speech encoder test mode
1
0
Speech decoder test mode
1
1
Acoustic device, A/D, Outputs audio data converted into digital signal from DO pin. D/A test mode Also inputs audio data input from DI pin to D/A converter. Inputting/outputting data is started at rising edge of first FSYNC (8-kHz external clock input) after execution of mode specification. At this time, clock output to DSP (SCLK) is stopped.
Note In the normal mode, do not set DRSTB to low level (during low period, serial interface with DSP is disabled). As well, set the output pins of driver IC to high-impedance state, because DRSTB input pin is connected with a pull-up resistor. Remark Analog loop back mode and DAI test mode cannot be specified at the same time. DAI test mode is set with TC1, TC2 (or ITC1, ITC2) and DRSTB pins. DAI test mode is entered at the rising edge of the DRSTB signal when both TC1 and TC2 pins (or ITC1 and ITC2 pins) are set as shown in Figure 2-14.
22
PD9930
Figure 2-14 Latch Timing of TC1, TC2 (or ITC1, ITC2)
TC1 (ITC1) TC2 (ITC2)
DRSTB
Figure 2-15 Example of System Configuration at Time of DAI Test Mode
Mobile equipment
PD9930
System simulator
25-Pin DSUB socket DAI DCLK DO
FSYNC MCLK MSTR MDAT
8 kHz Test command Microcontroller
DAI
DI TC1 TC2 DRSTB SCLK SEN SO SI REQB DSP (SP-CODEC)
Remark In the acoustic device test mode, REQB is ignored (both high and low levels). When DSPSEL = VDD (mode 1), SCLK and SEN are fixed to low, and when DSPSEL = GND (mode 2), fixed to high.
23
24
TC1 (ITC1) TC2 (ITC2) DRSTB REQB FSYNC (8 kHz) DCLK (104 kHz) DI don't care SCLK (256 kHz) SEN SO
Figure 2-16 Speech Encoder Test Mode (DSP Interface = MODE 1) (TC1 = 1, TC2 = 0)
"L"
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D12
D11
D10
D9
D8
D7
D6
D5
PD9930
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 2-17 Speech Encoder Test Mode (DSP Interface = Mode 2) (TC1 = 1, TC2 = 0)
TC1 (ITC1)
TC2 (ITC2)
"L"
DRSTB
REQB
FSYNC (8 kHz)
DCLK (104 kHz)
DI
don't care
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D12
D11
D10
D9
D8
D7
D6
D5
SCLK (256 kHz)
SEN
PD9930
SO
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
25
26
TC1 (ITC1) TC2 (ITC2) DRSTB REQB FSYNC (8 kHz) SCLK (256 kHz) SEN SI DCLK (104 kHz) DO
Figure 2-18 Speech Decoder Test Mode (DSP Interface = Mode 1) (TC1 = 0, TC2 = 1)
"L"
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PD9930
D12
D11
D10
D9
D8
D7
D6
D5
Figure 2-19 Speech Decoder Test Mode (DSP Interface = Mode 2) (TC1 = 0, TC2 = 1)
TC1 (ITC1)
"L"
TC2 (ITC2)
DRSTB
REQB
FSYNC (8 kHz)
SCLK (256 kHz)
SEN
SI
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DCLK (104 kHz)
DO
D12
D11 D10
D9
D8
D7
D6
D5
PD9930
27
28
TC1 (ITC1) TC2 (ITC2) DRSTB REQB FSYNC (8 kHz) SCLK (256 kHz) DCLK (104 kHz) DI DO
Figure 2-20 Acoustic Device Test Mode (DSP Interface = Mode 1) (TC1 = 1, TC2 = 1)
Note
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D12
D11
D10
D9
D8
D7
D6
D5
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D12
D11
D10
D9
D8
D7
D6
D5
PD9930
Note In DSP Interface = Mode 2, SCLK is fixed to high.
PD9930
3. TONE INTERVAL OUTPUT FUNCTION (TIMER TERMINAL)
When a tone is generated, an interval signal that indicates the tone intermittent state is output. The function is used, for example, to make the LED blink in synchronization with the ringer tone. Figure 3-1 Tone Interval Output Waveform
Tone generation
(1) Continuous tone
Tone generation Tone stop (31.25 ms) (31.25 ms)
(2) Intermittent tone (when 31.25 ms on/off)
Tone generation (200 ms)
(3) One-shot tone (200 ms one-shot)
Tone generation Tone stop (1 s) (1 s)
(4) GSM triple tone
29
PD9930
4. INTERNAL CONTROL FUNCTIONS
The PD9930 can control internal functions by commands from a microcontroller. Commands consist of 8bit data (D7 to D0) consisting of register address and setting data, and are written in the following internal registers.
Register name (1) (2) (3) (4) (5) (6) (7) (8) Voice send analog gain/receiver amplifier 2 control register (TXGCR) Voice receive analog gain control register (RXGCR) Voice send/receive digital gain control register (DGGSR) Digital signal processing control register (DSPCR) Tone frequency selection register (FRQSR) Expanded tone register (EXPR1/EXPR2) Tone control register (TONCR) Tone gain control register (TNGCR) Power up/down control Control Voice send/receive gain control
Digital input/output control Tone control
(9) Input/output amplifier control register (AMPCR) (10) Power up control command (PUPCMD) (11) Power down control command (PDWCMD) (12) Test control register (TSTCR)
Test mode control
Remarks 1. In the case of registers (1), (2), and (9) to (11), written contents are executed instantly. 2. For registers (3) to (8) and (12), since fetch execution is made by the internal clock (125 s interval), keep 125 s or more interval for write-in to the same register. If the write-in to the same register is executed continuously, the previous command may be ignored. 3. Even when in the stand-by mode, write-in to each internal register is possible (can be held), but the command written in the register is executed only after clearing the stand-by mode. 4.1 SEND/RECEIVE GAIN CONTROL An outline of send/receive gain control is shown in Figure 4-1. With the PD9930, the following send and receive gain control is possible.
Send/receive gain control Voice send gain control Pre-filter analog gain adjustment (0, -3 dB) Digital gain fine adjustment (0 to -2.8 dB, 0.4 dB steps) Voice receive gain control Receiver amplifier 1 analog gain adjustment (volume control) (0 to -31 dB, 1 dB steps) Digital gain fine adjustment (0 to -2.4 dB, 0.8 dB steps) Register used Voice send analog gain/receiver amplifier 2 control register (TXGCR) Voice send/receive digital gain control register (DGGSR) Voice receive analog gain control register (RXGCR) Voice send/receive digital gain control register (DGGSR)
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PD9930
Figure 4-1 Send/Receive Gain Control
Register address 0 0 0 1 1 0
TXGCR REC2PDB TXAG
Digital signal-processor 0 to -2.8 dB (0.4 dB steps) Voice send digital gain control
Pre-filter/mixer Microphone input or Accessory input Voice send analog gain control 0, -3 dB
A/D
BPF
SO
Register address 0 1 0 RXDG1 RXDG0
DGGSR TXDG2 TXDG1 TXDG0
Receiver amplifier 1 Voice receive analog gain control 0 to -31 dB (1 dB steps) Voice receive digital gain control 0 to -2.4 dB (0.8 dB steps)
Receiver output
D/A
LPF
SI
Register address 0 0 1 RXAG4 RXAG3
RXGCR RXAG2 RXAG1 RXAG0
31
PD9930
4.1.1 Voice Send Analog Gain/Receiver Amplifier 2 Control Register (TXGCR) This register controls pre-filter gain. It also controls receiver amplifier 2 power up/down as shown in Table 4-1 (Refer to 2.1.6 Power Up/Down Control). When power is down, the contents of the register area retained. After power is up, control continues as before power was down. Figure 4-2 Voice Send Analog Gain/Receiver Amplifier 2 Control Register
Register address D7 0 D6 0 D5 0 D4 1 D3 1 D2 0 TXGCR D1 REC2PDB D0 TXAG
REC2PDB 0 1
Receiver amplifier 2 power up/down specification Power down Power up
TXAG 0 1
Pre-filter analog gain specification Sets to 0 dB Sets to -3 dB
Table 4-1 Function Specification by Send Analog Gain/Receiver Amplifier 2 Control Register
Register address TXGCR Receiver amplifier 2 Power down Power down Power up Power up Voice send analog gain 0 dB -3 dB 0 dB -3 dB HEXNote M L Remarks At reset
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1
18H 18H 19H 98H 1AH 58H 1BH D8H
Note M: HEX value with MSB first L: HEX value with LSB first
32
PD9930
4.1.2 Voice Receive Analog Gain Control Register (RXGCR) This is a 5-bit register for controlling the analog gain (volume) of receiver amplifier 1. Figure 4-3 Voice Receive Analog Gain Control Register
Register address D7 0 D6 0 D5 1 D4 RXAG4 D3 RXAG3 RXGCR D2 RXAG2 D1 RXAG1 D0 RXAG0
RXAG4 to RXAG0 Receiver amplifier 1 gain specification 00000 to 11111 0 to -31 dB (1 dB steps)
33
PD9930
Table 4-2 Function Specifications by Voice Receive Analog Gain Control Register
Register address RXGCR Voice receive analog gain 0 dB -1 dB -2 dB -3 dB -4 dB -5 dB -6 dB -7 dB -8 dB -9 dB -10 dB -11 dB -12 dB -13 dB -14 dB -15 dB -16 dB -17 dB -18 dB -19 dB -20 dB -21 dB -22 dB -23 dB -24 dB -25 dB -26 dB -27 dB -28 dB -29 dB -30 dB -31 dB HEXNote M L Remarks
D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
20H 04H 21H 84H 22H 44H 23H C4H 24H 24H 25H A4H 26H 64H 27H E4H 28H 14H 29H 94H 2AH 54H 2BH D4H 2CH 34H 2DH B4H 2EH 74H 2FH F4H 30H 0CH 31H 8CH 32H 4CH 33H CCH 34H 2CH 35H ACH 36H 6CH 37H ECH 38H 1CH 39H 9CH 3AH 5CH 3BH DCH 3CH 3CH 3DH BCH 3EH 7CH 3FH FCH At reset
Note M: HEX value with MSB first L: HEX value with LSB first
34
PD9930
4.1.3 Voice Send/Receive Digital Gain Control Register (DGGSR) This is a 5-bit register for adjusting the gain of the digital signal processor. The gain of the send system and receive system can be fine-adjusted independently. Figure 4-4 Send/Receive Digital Gain Control Register
Register address D7 0 D6 1 D5 0 D4 RXDG1 D3 RXDG0
DGGSR D2 TXDG2 D1 TXDG1 D0 TXDG0
RXDG1 to RXDG0 Receive digital gain specification 00 to 11 0 to -2.4 dB (0.8 dB steps)
TXDG2 to TXDG0 Send digital gain specification 000 to 111 0 to -2.8 dB (0.4 dB steps)
35
PD9930
Table 4-3 Function Specifications by Voice Send/Receive Digital Gain Control Register
Register address DGGSR Voice receive digital gain 0 dB 0 dB 0 dB 0 dB 0 dB 0 dB 0 dB 0 dB -0.8 dB -0.8 dB -0.8 dB -0.8 dB -0.8 dB -0.8 dB -0.8 dB -0.8 dB -1.6 dB -1.6 dB -1.6 dB -1.6 dB -1.6 dB -1.6 dB -1.6 dB -1.6 dB -2.4 dB -2.4 dB -2.4 dB -2.4 dB -2.4 dB -2.4 dB -2.4 dB -2.4 dB Voice send digital gain 0 dB -0.4 dB -0.8 dB -1.2 dB -1.6 dB -2.0 dB -2.4 dB -2.8 dB 0 dB -0.4 dB -0.8 dB -1.2 dB -1.6 dB -2.0 dB -2.4 dB -2.8 dB 0 dB -0.4 dB -0.8 dB -1.2 dB -1.6 dB -2.0 dB -2.4 dB -2.8 dB 0 dB -0.4 dB -0.8 dB -1.2 dB -1.6 dB -2.0 dB -2.4 dB -2.8 dB HEXNote Remarks M L At reset 40H 02H 41H 82H 42H 42H 43H C2H 44H 22H 45H A2H 46H 62H 47H E2H 48H 12H 49H 92H 4AH 52H 4BH D2H 4CH 32H 4DH B2H 4EH 72H 4FH F2H 50H 0AH 51H 8AH 52H 4AH 53H CAH 54H 2AH 55H AAH 56H 6AH 57H EAH 58H 1AH 59H 9AH 5AH 5AH 5BH DAH 5CH 3AH 5DH BAH 5EH 7AH 5FH FAH
D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Note M: HEX value with MSB first L: HEX value with LSB first
36
PD9930
4.2 DIGITAL INPUT/OUTPUT CONTROL An outline of digital input/output control is shown in Figure 4-5. The PD9930 can control input and output of the digital signal processor as follows.
Digital input/output control Voice send data BPF operation processing execution/stop Connection and disconnection to tone output Voice send/ receive system Serial output terminal (SO) control Serial input terminal (SI) control Digital signal processing control register (DSPCR) Registers used
Caution You must not connect nor disconnect tone output voice send/receive system in the tone operation. It causes malfunction. Figure 4-5 Digital Input/Output Control
Register address 0 1 1 0 TXACT
DSPCR TNACT SOACT SIACT
Digital signal processor
DSP I/F
TXACT A/D 1 = ON BPF
SOACT 1 0 DGND SIACT SO
D/A Note TNACT 1 = ON
LPF 0 DGND 1
SI
Tone generator
Note Connected when TXACT = 0 and TNACT = 1.
37
PD9930
4.2.1 Digital Signal Processing Control Register (DSPCR) This is a 4-bit register for controlling digital signal processor input/output. Figure 4-6 Digital Signal Processing Control Register
Register address D7 0 D6 1 D5 1 D4 0 D3 TXACT DSPCR D2 TNACT D1 SOACT D0 SIACT
TXACT 0 1
Voice send data processing control Stops voice send data digital BPF processing. Executes voice send data digital BPF processing.
TNACT 0 1
Tone output control Disconnects tone output from voice send/receive systems. Connects tone output to voice send/receive systems.
SOACT 0 1
DSP interface output control Sets serial output (SO) at low level
Note
.
Outputs send data (or tone data) to the serial output (SO).
SIACT 0 1
DSP interface input control Sets serial input (SI) at low level
Note
.
Inputs receive data to serial input (SI).
Note Test Control Register can set serial input/output terminal at low level, too (refer to 4.4.1 Test Control Register (TSTCR)). Caution Before specification of SOACT bit, be sure to write "0" for SIOOFF bit of Test Control Register. If "0" isn't written for SIOOFF bit, serial output terminal is set at low level, regardless of SOACT bit.
38
PD9930
Table 4-4 Function Specification by Digital Signal Processing Control Register
Register address DSPCR Serial output control Note 2 Note 2 Control of output to D/A Note 3 Voice receive signal output Inhibiting command Inhibiting command Note 2 Note 2 Tone output Tone output Tone output HEXNote M L Remarks At reset
D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
60H 06H 61H 86H -- -- -- --
64H 26H
Voice receive signal + tone output 65H A6H Tone output 66H 66H
Voice receive signal + tone output 67H E6H Inhibiting command Inhibiting command -- -- Note 3 Voice receive signal output -- --
Voice send signal output Voice send signal output
6AH 56H 6BH D6H -- -- -- --
Inhibiting command Inhibiting command Voice send signal output Voice send signal output Tone output
6EH 76H
Voice receive signal + tone output 6FH F6H
Notes 1. M: HEX value with MSB first L: HEX value with LSB first 2. Stops voice send data processing and serial output. 3. Stops voice receive data serial input and tone output.
39
PD9930
4.3 TONE CONTROL An outline diagram of the tone generator is shown in Figure 4-7. Tone generation is by the tone 1 oscillation circuit and the tone 2 oscillation circuit. The tone 1 oscillation circuit generates high group frequency for DTMF and four types of single tones (tone 1 frequency). The tone 2 oscillation circuit generates low group frequency (tone 2 frequency) for DTMF. Dual tone is output by adding tone 1 frequency. In addition to registered tones, other frequencies can be registered. Also, GSM triple tone can be generated by special command. Examples of tone generation are shown in Figure 4-8. Tone control items are shown below.
Tone control Tone frequency Registered tone Specification of DTMF Single tone: 400 Hz, 425 Hz, 2 kHz, 2.6 kHz Selection of GSM triple tone User registration tone Registration of desired tone in 0.3 to 3.4 kHz range. (Single tone, dual tone) Registers used Tone frequency selection register (FRQSR) Tone control register (TONCR) Tone frequency selection register (FRQSR) Expanded tone register 1 (EXPR1) Expanded tone register 2 (EXPR2) Generation pattern Registered pattern Desired pattern Gain 31.25 ms intermittence, 200 ms intermittence, 250 ms intermittence, 500 ms intermittence, 1s intermittence, 200 ms one-shot tone Interrupted at desired interval by START/STOP command Tone gain control register (TNGCR) Tone control register (TONCR)
Control of tone output gain 0 to -30 dB (1 dB steps), -38.5 dB
40
Figure 4-7 Tone Control
Register address 1 0 0
FRQSR FRQSEL4 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
Register address Tone 1 oscillation circuit Tone 1 frequency 1209 Hz 1336 Hz 1477 Hz 1633 Hz 400 Hz 425 Hz 2000 Hz 2600 Hz 1 1 1
TNGCR TNGAIN4 TNGAIN3 TNGAIN2 TNGAIN1 TNGAIN0
-6 dB 3.1 dBm0
0 to -30 dB (1-dB steps) -38.5 dB LPF output (receive signal) (Only sign code) Ringer output
Expanded tone register 1
Expanded tone 1 frequency
TNACTNote To D/A START/ STOP Serial output
Tone 2 oscillation circuit Tone 2 frequency 697 Hz 852 Hz 770 Hz 941 Hz 3.1 dBm0 Expanded tone register 2 Expanded tone 2 frequency -9 dB - dB 0 1 Tone interval generation
Timer output
Note Digital signal processing control register bit 2 (Refer to Figure 4-6).
PD9930
Register address 1 0 1 TNMODE TNP2
TONCR TNP1 TNP0 START/ STOP
41
PD9930
Figure 4-8 Tone Generation Examples (a) When generating a busy tone (400 Hz single tone, 500 ms intermittence)
Busy tone generation DTMF "7" generation
(b) When generating DTMF "7" with continuous tone
Tone gain control register Set tone gain.
Tone gain control register Set tone gain.
Tone frequency selection register Set frequency to 400 Hz.
Tone frequency selection register Set frequency to DTMF "7".
Tone control register Select single tone Select 500 ms intermittent pattern. START/STOP = "1" (start)
Tone control register Select dual tone. Select continuous tone. START/STOP = "1" (start)
END
END
(c) When generating GSM triple tone
(d) When generating 200 ms intermittent user register tone (480 Hz single tone; coefficient = 0111011100B)
GSM triple tone generation
User register tone generation
Tone gain control register Set tone gain.
Tone gein control register Set tone gain.
Tone control register Select single tone Select GSM triple tone START/STOP = "1" (start)
Tone frequency selection register Specify "user register"
Expanded tone register 1 END "100110" (registration command) + registration data (lower order 2 bits) setting
Expanded tone register 1 Registration data (higher-order 8 bits) setting
Tone control register Select single tone. Select 200 ms intermittent pattern. START/STOP = "1" (start)
42
END
PD9930
4.3.1 Tone Frequency Selection Register (FRQSR) This is a 5-bit register for specifying tone 1 (high group frequency for DTMF and four types of single tones) and tone 2 (low group frequency for DTMF) frequency combinations. Figure 4-9 Tone Frequency Selection Register
Register address D7 1 D6 0 D5 0 D4 D3 FRQSR D2 D1 D0
FRQSEL4 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
FRQSEL4 to FRQSEL0 00000 to 10100
Tone frequency selection Refer to Table 4-5 Function Specification by Tone Frequency Selection Register.
Write operation in this register is instantaneously executed and retained when a command is received, but change of tone generation or generating tone is executed only when "1" is written for START/STOP control bit of the tone control register (refer to Figure 4-11 Tone Control Register). When a user registration tone is selected, the tone specified by the expanded tone register (refer to Figure 4-10 Expanded Tone Frequency Registration Procedure) is generated. Caution Do not input a command that sets a tone oscillation frequency after inputting a tone oscillation command (writing "1" to the START/STOP control bit of the tone control register).
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PD9930
Table 4-5 Function Specification by Tone Frequency Selection Register
Register address FRQSR DTMF function DTMF "1" DTMF "2" DTMF "3" DTMF "A" DTMF "4" DTMF "5" DTMF "6" DTMF "B" DTMF "7" DTMF "8" DTMF "9" DTMF "C" DTMF "" DTMF "0" DTMF "#" DTMF "D" Tone 1 frequency 1209 Hz 1336 Hz 1477 Hz 1633 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz 400 HzNote 2 425 HzNote 2 2 kHz
Note 2
HEXNote 1 Tone 2 frequency 697 Hz 697 Hz 697 Hz 697 Hz 770 Hz 770 Hz 770 Hz 770 Hz 852 Hz 852 Hz 852 Hz 852 Hz 941 Hz 941 Hz 941 Hz 941 Hz Indefinite value Indefinite value Indefinite value Indefinite value User registration M L Remarks
D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
80H 01H 81H 81H 82H 41H 83H C1H 84H 21H 85H A1H 86H 61H 87H E1H 88H 11H 89H 91H 8AH 51H 8BH D1H 8CH 31H 8DH B1H 8EH 71H 8FH F1H 90H 09H 91H 89H 92H 49H 93H C9H At reset 94H 29H -- -- -- -- -- --
2.6 kHzNote 2 User registration Inhibiting command Inhibiting command Inhibiting command
Notes 1. M: HEX value with MSB first L: HEX value with LSB first 2. This is single tone. When specifying this tone, be sure to specify the tone control register in the single tone mode (refer to Figure 4-11 Tone Control Register). Remark For DTMF tone generation, specify the tone control register in the dual tone mode (refer to Figure 4-11 Tone Control Register). If the register is specified in the single tone mode, only the high group tone (tone 1 frequency) is generated.
44
PD9930
4.3.2 Expanded Tone Registers (EXPR1, EXPR2) (1) Expanded Tone Frequency Registration Procedure The PD9930 can register desired tone frequencies (expanded tone frequencies) in 0.3 to 3.4 kHz range. Expanded tone register 1 (EXPR1) is for registering expanded tone 1 frequency (high group frequency for DTMF and single tone). Expanded tone register 2 (EXPR2) is for registering expanded tone 2 frequency (low frequency for DTMF). The frequency must be specified by 10-bit coefficient (2's complement). Registration of single tone is done with EXPR1 (single-tone generation is impossible by EXPR2) (refer to Figure 4-10 (a)). When registering dual tone, set high group in EXPR1 and low group in EXPR2. Write operation in this register can be executed by continuously writing the expanded tone registration command and expanded tone data command (refer to Figure 4-10). Once registered, the frequency is valid until reset or updated. Figure 4-10 Expanded Tone Frequency Registration Procedure (a) Expanded tone 1 frequency registration procedure <1> Set expanded tone 1 registration command in EXPR1. Expanded tone 1 registration command D7 EXPR1 1 0 0 1 1 0 EA1 EA0 D6 D5 D4 D3 D2 D1 D0
<2> Set higher-order 8 bits of expanded tone coefficient (expanded tone 1 data command) in EXPR1. Expanded tone 1 data command D7 EXPR1 EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 D6 D5 D4 D3 D2 D1 D0
Remark EA9 to EA0: Tone 1 frequency 10-bit coefficient (b) Expanded tone 2 frequency registration procedure <1> Set expanded tone 2 registration command in EXPR2. Expanded tone 2 registration command D7 EXPR2 1 0 0 1 1 1 EB1 EB0 D6 D5 D4 D3 D2 D1 D0
<2> Set higher-order 8 bits of expanded tone coefficient (expanded tone 2 data command) in EXPR2. Expanded tone 2 data command D7 EXPR2 EB9 EB8 EB7 EB6 EB5 EB4 EB3 EB2 D6 D5 D4 D3 D2 D1 D0
Remark EB9 to EB0: Tone 2 frequency 10-bit coefficient Caution After executing the expanded tone registration command, the next command is written as expanded tone data, so continuously execute the expanded tone data command.
45
PD9930
(2) Expanded Tone Data Determination Method The coefficient E of the tone frequency fe (0.3 to 3.4 kHz) to be generated is determined by the following formula. E = COS (2 fe/fs) fs = 8 kHz
Coefficient E: Sign bit 1 bit + 9 bits below the decimal point (Coefficient: 2's complement) Example When specifying 400 Hz single tone COS (2 x 400/8000) = COS ( x 0.1) = COS (0.3141592653......) = 0.951056516...... = (0.11110011X) b Next, the least significant bit is determined. When (0.111100110) b = 0.94921875 2 fe' x fs = COS-1 (0.94921875) = 0.320052983 fe' = 0.320052983 x fs/(2) fe' = 407.504115 When (0.111100111) b = 0.951071875 2 fe" x fs = COS-1 (0.951071875) = 0.314109559 fe" = 0.314109559 x fs/(2) fe" = 399.524415 Since fe" is nearest to 400 Hz, the coefficient to be registered is (0.111100111) b = (1E7) H. 0 EA9 1 EA8 1 EA7 1 EA6 1 EA5 0 EA4 0 EA3 1 EA2 1 EA1 1 EA0 (Higher-order 9 bits are determined.)
The error of oscillation frequency by rounding 10-bit coefficient is below 5 Hz (MAX. at 300 Hz 1.7 %) for all frequencies. About 1.67 % near 300 Hz (5 Hz) About 1.00 % near 500 Hz (5 Hz) About 0.40 % near 1 kHz (5 Hz) About 0.25 % near 2 kHz (5 Hz) About 0.16 % near 3 kHz (5 Hz) Coefficient is negative number in fe > 2.0 kHz.
46
PD9930
4.3.3 Tone Control Register (TONCR) This is a 5-bit register for controlling single tone/dual tone specification, generation pattern selection, and generation and stopping. Figure 4-11 Tone Control Register
Register address D7 1 D6 0 D5 1 D4 TNMODE D3 TNP2 TONCR D2 TNP1 D1 TNP0 D0 START /STOP
TNMODE Single tone/dual tone specification 0 1 Single tone mode Dual tone mode
Remarks At reset
TNP2 0 0 0 0 1 1 1 1
TNP1 0 0 1 1 0 0 1 1
TNP0 Generation pattern selection 0 1 0 1 0 1 0 1 Continuous tone generation 31.25 ms tone, 31.25 ms no tone repeated 200 ms tone, 200 ms no tone repeated 250 ms tone, 250 ms no tone repeated 500 ms tone, 500 ms no tone repeated 1 s tone, 1s no tone repeated GSM triple tone generated Note 1 200 ms interval tone generated (one shot tone)
Remarks At reset
START/STOP Tone generation/stop control 0 1 Stop ("1" "0", "0" "0" both valid) Note 2 Validation of tone ferquency selection register setting data, start of generation ("1" "1", "0" "1" both valid)
Remarks At reset
Notes 1. 950 Hz tone 333 ms, 1400 Hz tone 333 ms, 1800 Hz tone 333 ms, 1 s no tone repeated. 2. Do not input a command that sets a tone oscillation frequency after inputting a tone oscillation command (writing "1" to the START/STOP control bit of the tone control register). Remark When the regeneration pattern is specified as "110", it becomes GSM triple tone command, so tone generation forcibly enters single tone mode. Tone generation and change of a tone that is being generated is executed only when "1" is written for START/ STOP control bit (D0 bit) (refer to Figure 4-11 and Table 4-6).
47
PD9930
Table 4-6 Function Specification by Tone Control Register
Register address TONCR Tone control conditions Tone stop Continuous single tone generation 31.25 ms intermittent single tone generation 200 ms intermittent single tone generation 250 ms intermittent single tone generation 500 ms intermittent single tone generation 1 s intermittent single tone generation GSM triple tone generation 200 ms one-shot single tone generation Continuous dual tone generation 31.25 ms intermittent dual tone generation 200 ms intermittent dual tone generation 250 ms intermittent dual tone generation 500 ms intermittent dual tone generation 1 s intermittent dual tone generation 200 ms one-shot dual tone generation HEXNote M L
D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A0H 05H A1H 85H A3H C5H A5H A5H A7H E5H A9H 95H ABH D5H ADH B5H AFH F5H B1H 8DH B3H CDH B5H ADH B7H EDH B9H 9DH BDH BDH BFH FDH
Note M: HEX value with MSB first Remark X: Don't care
L: HEX value with LSB first
4.3.4 Tone Gain Control Register (TNGCR) This is a 5-bit register for controlling the tone output gain. Figure 4-12 Tone Gain Control Register
Register address D7 1 D6 1 D5 1 D4 D3 TNGCR D2 D1 D0
TNGAIN4 TNGAIN3 TNGAIN2 TNGAIN1 TNGAIN0
TNGAIN4 to TNGAIN0 00000 to 11111
Tone gain selection (Refer to Table 4-7 Function Specification by Tone Gain Control Register). 0 to -30 dB (1 dB steps), -38.5 dB
48
PD9930
Table 4-7 Function Specification by Tone Gain Control Register
Register address TNGCR Tone gain 0 dB -1 dB -2 dB -3 dB -4 dB -5 dB -6 dB -7 dB -8 dB -9 dB -10 dB -11 dB -12 dB -13 dB -14 dB -15 dB -16 dB -17 dB -18 dB -19 dB -20 dB -21 dB -22 dB -23 dB -24 dB -25 dB -26 dB -27 dB -28 dB -29 dB -30 dB -38.5 dB HEXNote M L Remarks
D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
E0H 07H E1H 87H E2H 47H E3H C7H E4H 27H E5H A7H E6H 67H E7H E7H E8H 17H E9H 97H EAH 57H EBH D7H ECH 37H EDH B7H EEH 77H EFH F7H F0H 0FH F1H 8FH F2H 4FH F3H CFH F4H 2FH F5H AFH F6H 6FH F7H EFH F8H 1FH F9H 9FH FAH 5FH FBH DFH FCH 3FH FDH BFH FEH 7FH FFH FFH At reset
Note M: HEX value with MSB first L: HEX value with LSB first
49
PD9930
4.4 TEST MODE CONTROL The PD9930 has the following test functions.
Test function DAI test function This test function is stipulated in GSM11.10. Test mode selection can be controlled by external terminal (TC1 or TC2) or internal register (ITC1, ITC2). Send data after BPF processing is input to LPF. SO, SI, SCLK and SEN terminals can be set at low level. Registers used Test control register (TSTCR)
Analog loopback function DSP interface input/ output control function
An outline of test mode control is shown in Figure 4-13.
50
PD9930
Figure 4-13 Test Mode Operation
(a) DAI (speech encoder test mode)
(b) DAI (speech decoder test mode)
Mobile Station
Mobile Station
PD9930
DSP I/F DSP
PD9930
DSP I/F DSP
SO
speech encoder
TX
SI
speech decoder
RX
DAI DI TC1 TC2 1 0 System simulator
DAI DO TC1 TC2 0 1 System simulator
(c) DAI (A/D, D/A test mode)
(d) Analog loopback mode
Mobile Station
PD9930
PD9930
DAI A/D BPF DO A/D BPF
D/A
LPF
DI TC1 TC2 1 1
System simulator
D/A
LPF
51
PD9930
4.4.1 Test Control Register (TSTCR) This is a 5-bit control register for selecting the test mode. ITC1, ITC2 become valid at the rising edge of DRSTB. For the precautions when using DAI, refer to 2.1.9 DAI (Digital Audio Interface). Figure 4-14 Test Control Register
Register address D7 1 D6 1 D5 0 D4 TCMODE D3 ITC2 TSTCR D2 ITC1 D1 LOOPBK D0 SIOOFF
TCMODE DAI test mode control method selection 0 1
Remarks
Specification of test mode by external terminals TC1 and TC2 At reset Specification of test mode by test control registers ITC1 and ITC2
ITC2 0 0 1 1
ITC1 0 1 0 1
DAI test mode specification Normal operation Speech encoder test mode Speech decoder test mode Acoustic device, A/D, D/A test mode
Remarks At reset
LOOPBK 0 1
Analog loopback specification Normal operation Analog loopback
Remarks At reset
SIOOFF 0 1
DSP interface input/output terminal control Normal operation
Remarks
Setting of terminals SO, SI, SCLK, and SEN to low level At reset
Remark The analog loopback mode and the DAI test mode cannot be specified at the same time.
52
PD9930
5. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (TA = 25C, DGND = AGND1 to AGND4 = 0 V)
Item Supply Voltage Analog Input Voltage Digital Input Voltage Analog Output Pin Applied Voltage Digital Output Pin Applied Voltage Operating Ambient Temperature Storage Temperature Symbol VDD VAIN VDIN VAOUT VDOUT TA Tstg Conditions AVDD1, AVDD2, DVDD All analog input pins All digital input pins All analog output pins All digital output pins Ratings -0.3 to +5.5 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -30 to +85 -65 to +150 Unit V V V V V C C
Cautions 1. Connect the AGND1 through AGND4 pins and DGND pin to an analog ground line near PD9930 pins. Connect the DVDD, AVDD1, AVDD2 pins to an analog power supply line near PD9930 pins. 2. Do not connect output (and bidirectional) pins each other. Do not connect output (or bidirectional) pins directly to the VDD, VCC, or GND line. However, open drain pin and open collector pin can be directly connected to VDD, VCC, or GND line. If timing design is made so that no signal conflict occurs, three-state pins can also be connected directly to three-state pins of external circuit. 3. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics.
53
PD9930
RECOMMENDED OPERATING RANGE (TA = -30 to +85C) (1) DC Condition
Item Supply Voltage High Level Input Voltage Low Level Input Voltage Analog Input Voltage Microphone Input Analog Input Voltage Gain Setting Range Load Resistance Load Capacitance Accessory Input Analog Input Voltage Gain Setting Range Load Resistance Load Capacitance Pre-filter + Mixer Input Analog Input Voltage Accessory Output Load Resistance Load Capacitance Receiver 1 Output Load Resistance Load Capacitance Receiver 2 Output Analog Input Voltage Gain Setting Range Load Resistance Load Capacitance Reference Voltage Output Load Capacitance CLACOM XACOMO, RACOMO 0.2 10 VREC2 GREC2 RLREC2 CLREC2 REC2ISet with external resistor 60 nF series 2 k series - 2 60 1.2 +10 Vp-p dB k nF RLREC1 CLREC1 100 20 k pF RLAUXO CLAUXO 100 100 k pF VMIXI MIXI 1.2 Vp-p VAUXI GAUXI RLAUXI CLAUXI XAUXI- Set with external resistor Includes gain setting resistance 0 300 20 1.2 10 Vp-p dB k pF VMIC GMIC RLMIC CLMIC Differential: MICI+, MICI- Set with external resistor Includes gain setting resistance 15 50 20 1.2 33 Vp-p dB k pF Symbol VDD VIH VIL VIA Conditions AVDD1, AVDD2, DVDD All digital input pins All digital input pins All analog input pins MIN. 2.7 0.7 VDD 0 0.6 TYP. 3.0 MAX. 3.6 VDD 0.3 VDD 1.8 Unit V V V V
F
(2) Frame Signal (FSYNC) and Reset Signal (RESETB)
Item FSYNC Frequency FSYNC High Level Width FSYNC Low Level Width FSYNC Rise Time FSYNC Fall Time RESETB Low Level Width Symbol fs tWHS tWLS tr tf tRSL 260 Conditions MIN. 7.995 2.0 2.0 20 20 TYP. 8.000 MAX. 8.005 Unit kHz
s s
ns ns ns
54
PD9930
(3) Microcontroller Interface
Item MCLK Cycle Time MCLK High Level Width MCLK Low Level Width MCLK Rise Time MCLK Fall Time MDAT Setup Time to MSTR MDAT Hold Time from MCLK MSTR High Level Width MCLK Setup Time to MSTR MSTR Setup Time to MCLK Symbol tMCY tMCH tMCL tMR tMF tSUMDA tHMDA 50 50 Conditions MIN. 240 100 100 20 20 TYP. MAX. Unit ns ns ns ns ns ns ns
tWMST tSUMCK tSUMST
320 0 100
ns ns ns
(4) DSP Interface
Item SI Setup Time to SCLK SI Hold Time from SCLK Symbol tSUSI tHSI Conditions MIN. 200 200 TYP. MAX. Unit ns ns
(5) DAI
Item DI Setup Time to DCLK DI Hold Time from DCLK TC1, TC2 Rise Time TC1, TC2 Fall Time DRSTB Low Level Width DRSTB Rise Time DRSTB Fall Time DAI Mode Setting Time 1 DAI Mode Setting Time 2 REQB Low Level Width REQB High Level Width REQB Rise Time REQB Fall Time Symbol tSUDI tHDI tTR tTF tDRSL tDRR tDRF tTCF tTCR tDRQL tDRQH tDRQR tDRQF 60 260 130 130 20 20 Conditions MIN. 200 200 50 50 130 20 20 TYP. MAX. Unit ns ns ns ns
s
ns ns ms
s s s
ns ns
55
PD9930
CAPACITANCE (TA = 25C)
Item Digital Output Pin Capacitance Digital Input Pin Capacitance Symbol COD f = 1 MHz Conditions MIN. TYP. MAX. 20 Unit pF
CID
f = 1 MHz
20
pF
DC CHARACTERISTICS (TA = 25C, V (1) Current Consumption
Item Circuit Current in Normal Mode Symbol IDD1
DD
= 2.7 to 3.6 V (GND standard))
Conditions Microphone input (1020 Hz: -10 dBm0) Accessory input: Power down serial input (1020 Hz: -10 dBm0) Accessory output: Power up Receiver 1, 2: Power up Microphone input (1020 Hz: -10 dBm0) Accessory input: Power down serial input (1020 Hz: -10 dBm0) Accessory output: Power up Receiver 1, 2: Power up DI, DRSTB, TC1, TC2: Open FSYNC: 8 kHz Other digital input pins: 0 or VDD
MIN.
TYP. 7.0
MAX. 9.0
Unit mA
Circuit Current in DAI Operation
IDD2
7.5
10.0
mA
Circuit Current in Standby Mode
IDD3
50
100
A
(2) Digital Part
Item Digital Input Leak Current Symbol ILH ILL Pull-Up/Down Current Low Level Output Voltage High Level Output Voltage IIL VOL VOH VI = VDD VI = 0 VDD = 3.3 V, 0 VI VDD IOL = 2.0 mA IOH = -2.0 mA 2.4 -1.0 100 0.4 Conditions MIN. TYP. MAX. 1.0 Unit
A A A
V V
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PD9930
(3) Analog Part
Item Pre-filter + Mixer Volume Range Volume Accuracy Cross-Talk 1 between Input Channels GPRF GPRF CTIN1 Volume 0 dB standard Microphone input amplifier: Power down MICI = 1.2 Vp-p XAUXI- = 0 Vp-p Accessory input gain setting: 0 dB Accessory input amplifier: Power down MICI = 0 Vp-p XAUXI- = 1.2 Vp-p Accessory input gain setting: 0 dB -3 -3.2 -3.0 0 -2.8 -45 dB dB dB Symbol Conditions MIN. TYP. MAX. Unit
Cross-Talk 2 between Input Channels
CTIN2
-45
dB
Accessory Output Maximum Output Voltage Receiver 1 Output Maximum Output Voltage Volume Range Volume Accuracy VR1MAX 1.2 Vp-p VAMAX 1.2 Vp-p
GREC1 GREC1 Volume: 0 to -16 dB VolumeNote: -17 to -31 dB
-31 -1.5 -2.0 -1.0 -1.0
0 -0.5 0.0
dB dB dB
Receiver 2 Output Maximum Output Voltage Reference Voltage Output Output Voltage VACOM XACOMO, RACOMO 1.2 V VR2MAX Distortion factor 4 % (MAX.) 4 Vp-p
Note Simple decrease in the gain due to drop of volume is guaranteed. (4) Tone Generator
Item Output Signal Level Symbol VTN1 VTN2 Frequency Deviation Distortion Factor Tone Volume Range Tone Volume Accuracy FTN TNSD GTN GTN Volume: 0 to -30 dB (1 dB steps) Tone 1 Tone 2 0.3 to 3.4 kHz Accessory output Conditions MIN. -2.93 -5.93 -5 30 -38.5 -1.4 -1.0 0 -0.8 TYP. MAX. -2.73 -5.73 +5 Hz dB dB dB Unit dBm0
57
PD9930
AC CHARACTERISTICS (1) DSP Interface (TA = -30 to +85C, V
Item SCLK Cycle Time SCLK High Level Width SCLK Low Level Width SCLK Rise Time SCLK Fall Time SCLK Delay Time from FSYNC SEN Delay Time from FSYNC SEN Delay Time from SCLK : Mode 1 SEN Delay Time from SCLK : Mode 2 SO Output Delay Time from SCLK : Mode 1 SO Output Delay Time from SCLK : Mode 2 Symbol tSCY tSCH tSCL tSR tSF tDSCLK
DD
= 2.7 to 3.6 V, CL = 100 pF)
Conditions MIN. TYP. 3906 1953 1953 20 20 1.0 MAX. Unit ns ns ns ns ns
s
ns
tDSENR
80
tDSENF
80
ns
tDSO
40
ns
(2) DAI (TA = -30 to +85C, V
Item DCLK Cycle Time DCLK High Level Width DCLK Low Level Width DCLK Rise Time DCLK Fall Time DCLK Delay Time from FSYNC DO Output Delay Time from DCLK
DD
= 2.7 to 3.6 V, CL = 100 pF)
Conditions MIN. TYP. 9615 4808 4808 20 20 200 MAX. Unit ns ns ns ns ns ns
Symbol tDCY tDCH tDCL tDR tDF tDDCLK
tDDO
200
ns
(3) Others (Digital Output) (TA = -30 to +85C, V
Item TIMER/RINGER Rise Time TIMER/RINGER Fall Time Symbol tDDR tDDF
DD
= 2.7 to 3.6 V, CL = 100 pF)
MIN. TYP. MAX. 50 50 Unit ns ns
Conditions TIMER pin and RINGER pin TIMER pin and RINGER pin
58
PD9930
Frame signal (FSYNC)
1/fs tWHS tr
FSYNC
tf
tWLS
Remark During normal operation or the power up/down sequence, be sure to input the frame signal. Reset signal (RESETB)
RESETB
tRSL
Remarks 1. The reset signal is input as it is without shaping, so take full precautions against noise. 2. A power on reset circuit is not incorporated, so be sure to set RESET to low after turning the power on. Microcontroller interface timing
tWMST
MSTR
tMCY
tMCH
tSUMCK
tSUMST
MCLK
tMR tSUMDA tHMDA
tMCL
tMF
MDAT
D0
D1
D2
D6
D7
D0
Remark D0 to D7: Microcontroller command (LSB first)
59
PD9930
DSP interface timing (mode 1)
SCLK
tDSCLK
tSCY
tSCL
tSF
tSCH
tSR
FSYNC
tDSENR
tDSENF
SEN
tDSO
SO
D15
D14
D13
D1
D0
tSUSI
tHSI
SI
don't care
D15
D14
D13
D0
don't care
DSP interface timing (mode 2)
SCLK
tDSCLK
tSCY
tSCH
tSR
tSCL
tSF
FSYNC
tDSENF
tDSENR
SEN
tDSO
SO
D15
D14
D13
D1
D0
tSUSI
tHSI
SI
don't care
D15
D14
D13
D0
don't care
60
PD9930
DAI input timing
FSYNC
tDDCLK
tDCY
tDCH
tDR
DCLK
tSUDI
tHDI
tDCL
tDF
DI
D12
D11
D10
D9
D8
D7
Remark D12 to D0: Input data (MSB first) DAI output timing
FSYNC
tDDCLK
tDCY
tDCH
tDR
DCLK
tDDO
tDCL
tDF
DO
D12
D11
D10
D9
D8
D7
Remark D12 to D0: Output data (MSB first)
61
PD9930
TC1, TC2, DRSTB input timing
TC1, TC2
tTR, tTF
tTCF tDRF
tTCR tDRR
tTR, tTF
DRSTB
tDRSL
TIMER, RINGER output timing
tDDR
tDDF
TIMER, RINGER
REQB input timing
tDRQF
tDRQR tDRQH
REQB
tDRQL
62
PD9930
TRANSMISSION CHARACTERISTICS Transmission characteristics are as indicated below unless otherwise specified. * Analog input Analog input signal (-10 dBm0, 1020 Hz) accessory input part Accessory input: Set gain 0 dB Microphone input: Power down Pre-filter + mixer: Set gain 0 dB * Analog output Analog output signal accessory output part Receiver output: Power down * Digital gain set Send and receive: 0 dB * Digital input signal level: 0 dBm0 * TA = 25C, V
DD
= 2.7 to 3.6 V (GND standard)
(1) Send/Receive Zero Transmission Level (0 dBm0 level)
Item Send Zero Transmission Level Receive Zero Transmission Level Symbol V0TLPX 600 standard 600 standard Conditions MIN. TYP. -8.4 MAX. Unit dBm
V0TLPR
-8.4
dBm
(2) Gain Characteristics
Item Send Gain Deviation Receive Gain Deviation Send Gain Deviation Temperature Power Fluctuation Receive Gain Deviation Temperature Power Fluctuation Symbol GX GR GX Conditions MIN. -0.5 -0.5 -0.4 TYP. MAX. +0.5 +0.5 +0.4 Unit dB dB dB
GR
-0.4
+0.4
dB
(3) Transmission Loss Level
Item Send Transmission Loss Level Symbol GTX +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 Receive Transmission Loss Level GTR +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 Conditions MIN. -0.4 -0.6 -1.2 -0.4 -0.6 -1.2 TYP. MAX. +0.4 +0.6 +1.2 +0.4 +0.6 +1.2 Unit dB dB dB dB dB dB
63
PD9930
(4) Transmission Gain Frequency Characteristics
Item Send Transmission Gain Frequency Characteristics Symbol GRX1 GRX2 GRX3 GRX4 GRX5 GRX6 GRX7 Receive Transmission Gain Frequency Characteristics GRR3 GRR4 GRR5 GRR6 GRR7 60 Hz 200 Hz 0.3 to 3.0 kHz 3.2 kHz 3.4 kHz 4.0 kHz 4.6 kHz or more 0.3 to 3.0 kHz 3.2 kHz 3.4 kHz 4.0 kHz 4.6 kHz or more -0.3 -0.65 -0.8 -2.5 -0.3 -0.65 -0.8 Conditions MIN. TYP. MAX. -23 0 +0.3 +0.3 0 -14 -28 +0.3 +0.3 0 -14 -28 Unit dB dB dB dB dB dB dB dB dB dB dB dB
(5) Noise Characteristics
Item Send Noise Symbol NXC Conditions Microphone power down, XAUXI- ACOM, gain 0 dB, C message filter C message filter, input +0 code from SI MIN. TYP. MAX. 25 -65 25 -65 Single Frequency Noise Cross-Talk between Send and Receive Channels NSF CTTR Send input Receive output No sidetone pass, microphone power down input 0 dBm0 and 1020 Hz from XAUXI- input +0 code from SI No sidetone pass, microphone power down XAUXI- ACOM input 0 dBm0 and 1020 Hz from SI VDD 100 mV0-p signal application f = 0 to 3.4 kHz 30 -50 -60 Unit dBrnc0 dBm0c dBrnc0 dBm0c dBm0 dB
Receive Noise
NRC1
Cross-Talk between Receive and Send Channels
CTRT
-60
dB
Power Supply Voltage Variation Rejection
PSRR
dB
64
PD9930
(6) Distortion Factor Characteristics
Item Send Channel Total Power Distortion Factor
Symbol SDX 0 to -10 dBm0 -40 dBm0 -45 dBm0
Conditions
MIN. 35 25 20 35 25 20
TYP.
MAX.
Unit dB
Receive Channel Total Power Distortion Factor
SDR
0 to -10 dBm0 -40 dBm0 -45 dBm0
dB
Absolute Delay Delay Distortion Frequency Characteristics
DA DO
XAUXI- RAUXO XAUXI- RAUXO 500 Hz 600 Hz 1 kHz 2.6 kHz 2.8 kHz
550 1.40 0.70 0.20 0.20 1.40
s
ms
Send Transmission Gain Frequency Characteristics 1 (GRX)
5 0 -5 -10 -15 Send transmission gain (dB) -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Frequency (kHz)
65
PD9930
Send Transmission Gain Frequency Characteristics 2 (GRX)
0.1
0
-0.1
-0.2
Send transmission gain (dB)
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9 0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
Frequency (kHz)
Receive Transmission Gain Frequency Characteristics 1 (GRR)
5 0 -5 -10 -15 -20 Receive transmission gain (dB) -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
66
Frequency (kHz)
PD9930
Receive Transmission Gain Frequency Characteristics 2 (GRR)
0.1
0
-0.1
-0.2
Receive transmission gain (dB)
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9 0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
Frequency (kHz)
67
PD9930
Send/receive zero transmission level (0 dBm0 level) is explained below for your reference. (a) Send zero transmission level Analog output signal level at which the digital input signal level of the D/A converter becomes 0 dBm0. (b) Receive zero transmission level Analog input signal level at which the digital output signal level of the A/D converter becomes 0 dBm0. (c) Analog signal level (dBm) The conversion expression of the amplitude voltage of a signal and an analog signal level is as follows: X = 10 logW X: analog signal level (dBm) W: analog signal power (mW) W = (V2/R) x 103 V: effective value of analog signal (AC) (Vrms) R: resistance () With the PD9930, the signal voltage (effective value) can be calculated if R = 600 and X = -8.4 dBm are substituted. W = 0.1445 (mW) V = 0.294 (Vrms) To calculate V0-p, multiply the signal voltage (effective value) by 2. V0-p = 0.416 (V) (d) Digital signal level (dBm0) Signal level where the level of the full swing of the digital output value of the A/D converter and the digital input value of the D/A converter is considered to be 3.17 dBm0 (the amplitude of the analog signal is 1.2 Vp-p where the gain of the microphone input or accessory input is 0 dB). This diagram indicates the range in which adjustments can be made by using each amplifier and gain control function. Example: Input level at which digital output of linear codec is -10 dBm0 is -33 dBm. (Conditions) Microphone amplifier gain during microphone input: 15 dB Analog gain control: 0 dB Digital gain control: 0 dB Output level at which digital input of linear codec is -10 dBm0 is -18.4 dBm. (Conditions) During receiver output Analog gain control: 0 dB Digital gain control: 0 dB
68
PD9930
Voice send level diagram (microphone input)
+ Vref - [dBm] 0
Analog gain control
A/D
Digital gain control
[dBm0] 15 to 33 dB -10 0 dB or -3 dB 0 to -2.8 dB (0.4 dB steps) -10 dBm0 -20 -33.4 dBm -15.8 dBm0 -10 0
-30
-20
-40 -41.4 dBm -50
-30
-40
-60
-50
-60
Remarks 1. Thick line: Indicates case where gain of microphone amplifier is set to 15 dB, gain of analog gain control to 0 dB, and gain of digital gain control to 0 dB. Thin line: Indicates case where gain of microphone amplifier is set to 33 dB, gain of analog gain control to -3 dB, and gain of digital gain control to -2.8 dB. 2. Overload level: 3.17 dBm0.
69
PD9930
Voice receive level diagram (receiver output)
Receiver 1 [dBm] 0
Analog gain control
D/A
Digital gain control 0 to -2.4 dB (0.8 dB steps)
0 to -31 dB (1 dB steps)
[dBm0] 0
-10 -18.4 dBm -20 -10 dBm0
-10
-30
-20
-40
-30
-50 -51.8 dBm -60
-40
-50
-60
Remarks 1. Thick line: Indicates case where gain of analog gain control is set to 0 dB and gain of digital gain control to 0 dB. Thin line: Indicates case where gain of analog gain control is set to -31 dB and gain of digital gain control to -2.4 dB. 2. Overload level: 3.17 dBm0.
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PD9930
Voice send level diagram (accessory input)
+ Vref - [dBm] 0
Analog gain control
A/D
Digital gain control
[dBm0] 0 to 10 dB -10 -18.4 dBm -20 -15.8 dBm0 -30 -28.4 dBm -30 0 dB or -3 dB 0 to -2.8 dB (0.4 dB steps) -10 dBm0 -10 0
-20
-40
-50
-40
-60
-50
-60
Remarks 1. Thick line: Indicates case where gain of microphone amplifier is set to 0 dB, gain of analog gain control to 0 dB, and gain of digital gain control to 0 dB. Thin line: Indicates case where gain of microphone amplifier is set to 10 dB, gain of analog gain control to -3 dB, and gain of digital gain control to -2.8 dB. 2. Overload level: 3.17 dBm0.
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PD9930
Voice receive level diagram (accessory output)
[dBm] 0
Accessory output 0 dB (fix)
D/A
Digital gain control 0 to -2.4 dB (0.8 dB steps)
[dBm0] 0
-10 -18.4 dBm -20 -20.8 dBm -30 -10 dBm0
-10
-20
-40
-30
-50
-40
-60
-50
-60
Remarks 1. Thick line: Indicates case where gain of digital gain control is set to 0 dB. Thin line: Indicates case where gain of digital gain control is set to -2.4 dB. 2. Overload level: 3.17 dBm0.
72
6. APPLIED CIRCUIT EXAMPLE
1 F 12 k 100 k to 500 k 0.1 F 22 MICO 21 MICI- 20 MICI+
1 F
8 kHz
From RESET circuit
From DSP
19 AGND4
18 AGND3
17 AGND2
16 AGND1
15 DGND
14 FSYNC
13 RESETB
12 REQB
23 MIXI 300 k Accessory input 2.2 F + - 100 k to 300 k 25 XAUXI- 26 XACOMI 0.1 F 27 XACOMO 28 RACOMO 0.1 F Note 29 RACOMI 30 REC2O+ 31 REC2O- 100 k to 900 k 0.1 F 33 REC2I- RAUXO REC1O 100 k to 300 k 32 IC 24 XAUXO
DSPSEL 11
VDD (mode 1) or GND (mode 2)
RINGER 10 Low-current drive LED TIMER 9
TC2
8 7 6 5 4 3 2 1 Microcontroller DSUB socket (25 pin)
+ 2.2 F -
PD9930G-22
TC1 DCLK DO DI DRSTB MCLK MDAT
MSTR
SCLK
AVDD1
AVDD2
TEST
DVDD
SEN
SO
SI
34 300 k
35
36
37
38
39
40
41
42
43
44
PD9930
0.1 F
Accessory output + 4.7 F -
+ 4.7 F - 0.1 F
0.1 F
DSP
To REQB
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Note When connecting a dynamic receiver, use a drive amplifier.
PD9930
7. PACKAGE DRAWINGS 44 PIN PLASTIC QFP ( 10)
A B
33 34
23 22
detail of lead end
D
C
S
44 1
12 11
F
G
H
I
M
J K
P
N L
M
55
Q
P44G-80-22-2 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 13.6 0.4 10.0 0.2 10.0 0.2 13.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 1.0 0.2 0.15+0.10 -0.05 0.15 1.45 0.1 0.05 0.05 1.65 MAX. INCHES 0.535+0.017 -0.016 0.394+0.008 -0.009 0.394+0.008 -0.009 0.535+0.017 -0.016 0.039 0.039 0.014+0.004 -0.005 0.006 0.031 (T.P.) 0.071+0.008 -0.009 0.039+0.009 -0.008 0.006+0.004 -0.003 0.006 0.057+0.005 -0.004 0.002 0.002 0.065 MAX.
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
74
PD9930
8. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met for soldering conditions of the PD9930. For more details, refer to our document "Semiconductor Device Mounting Technology Manual" (C10535E). Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. Type of Surface Mount Device
PD9930G-22: 44-pin plastic QFP (10 x 10 mm)
Soldering process Infrared ray reflow Soldering conditions Peak temperature of package surface: 235C or below, Reflow time: 30 seconds or below (210C or higher), Number of reflow processes: MAX. 2 Exposure limitNote: 7 days (10 hours pre-baking is required at 125C afterwards) Peak temperature of package surface: 215C or below, Reflow time: 40 seconds or below (200C or higher), Number of reflow processes: MAX. 2 Exposure limitNote: 7 days (10 hours pre-baking is required at 125C afterwards) Wave soldering Soldering bath temperature: 260C or below, Reflow time: 10 seconds or below, Number of reflow processes: 1 Preheating temperature: 120C MAX. (package surface temperature) Exposure limitNote: 7 days (10 hours pre-baking is required at 125C afterwards) WS60-107-1 Symbol IR35-107-2
VPS
VP15-107-2
Partial heating method Terminal temperature: 300C or below, Time: 3 seconds or below (Per one side of the device).
--
Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25C and relative humidity at 65 % or less. Caution Do not apply more than one soldering method at any one time, except for "Partial heating method".
75
PD9930
[MEMO]
76
PD9930
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
77
PD9930
[MEMO]
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
78

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